In semiconductor fabrication, many semiconductor chips are fabricated together on a single wafer. Fabrication of these chips generally involves forming several different structures on the wafer, including wiring layers, active devices and passive devices. These structures can be fabricated using conventional lithography, etching and deposition processes.
Scaling in semiconductor fabrication can be problematic, however, particularly, high-speed complementary metal-oxide semiconductor (CMOS) scaling beyond the 10 nm node. This scaling can be different beyond the 10 nm node because of pressure to lower Vdd due to reliability at very small conductor-to-conductor spaces, e.g., drain-contact-to-gate. These spaces are demanded to enable continued circuit density gains for lower power per function and increased function per die.
Current approaches to reduce some scaling pressure include the use of Vertical Transport CMOS (VTCMOS) structures. VTCMOS includes using uniform layout vertical transistors on pitch. Other approaches to address the scaling problem include horizontal FinFET CMOS structures with p+ and n+ current vectors oriented at 45-degree angles, with respect to one-another, in order to obtain mobility improvement.